complex programmable logic gadgets (CPLDs) contain the building blocks for numerous 7400-serries logic ICs. total circuits can be designed on a PC as well as then uploaded to a CPLD for immediate implementation. A microcontroller linked to a CPLD is like a microcontroller paired with a reprogrammable circuit card as well as a completely stocked electronics store.

At very first we weren’t sure of the wide charm as well as application of CPLDs in hobbyist projects, however we’ve been convinced. A custom logic gadget can get rid of days of reading datasheets, discovering the perfect logic IC combination, as well as then waiting on chips to arrive. Circuit boards are easier with CPLDs since a single chip with programmable pin placement can replace 100s of private logic ICs. Circuit errors can be corrected by uploading a new design, rather than etching as well as stuffing a new circuit board. CPLDs are fast, with reaction times starting at 100MHz. in spite of their extreme versatility, CPLDs are a mature innovation with chips starting at $1.

We’ve got a home-etchable, self programming advancement board to get you started. Don’t worry, this board has a serial port interface for working with the CPLD, as well as doesn’t need a separate (usually parallel port) JTAG programmer.

Intro to CPLDs

When to utilize a CPLD

Consider utilizing a CPLD when a style requires more than one 7400 series logic ICs. A CPLD will be cheaper, faster, as well as can be programmed with your perfect pin-out configuration for easier PCBs.

Use a CPLD in tricky styles that may need a number of iterations. It’s easier to style a new circuit in software application as well as upload it to the CPLD than it is to design, etch, as well as stuff a new circuit board.

For maximum speed as well as immediate response, select a CPLD. The difference in speed is amazing; CPLDs begin at a 100MHz, while microcontrollers respond to interrupts at a few MHz. CPLD styles type circuits that react to outside stimulus, reactions happen almost instantaneously. A microcontroller executes code to react to events, even interrupt routines have comparatively high latency.

CPLD vs FPGA

FPGAs are much better understood than CPLDs, however they share many characteristics. This analogy isn’t perfect, however we like it: where FPGAs are a reprogrammable processor core, a CPLD is a reprogrammable circuit card or breadboard. FPGAs replace microcontrollers, memory, as well as other components. CPLDs take in logic ICs, as well as work well with a microcontroller.

Manufacturers

Altera as well as Xilinx, the biggest CPLD manufacturers, are much better understood for their FPGAs. Lattice Semiconductor is one more big CPLD manufacturer with less neighborhood following. Atmel makes pin-compatible versions of old industry-standard CPLDs.

If you plan to work at 5volts, your choices are limited. Xilinx XC9500 CPLDs are still offered as new old stock, however expense four times more than newer 3.3volt equivalents. Atmel’s ATF1502 series works at 5volts, however they don’t offer a free advancement environment.

At 3.3volts there’s more options, however new CPLDs progressively have a core that runs at 2.5volts, 1.8volts, or lower. The Altera MAXII as well as the Xilinx XC9500XL series are most likely the most prominent 3.3volt CPLDs. Xilinx likewise makes the CoolrunnerII CPLD, however it only is available in a TQFP bundle as well as needs a separate 1.8volt supply for the core.

Packages

Most manufacturers offer one or two CPLDs in a hobbyist friendly PLCC 44 package, though this is starting to disappear. PLCC is an SOIC-sized surface install chip with pins on all four sides. PLCC44 sockets are commonly offered in through-hole as well as SMD versions. Unfortunately, newer CPLD households are starting to get rid of the PLCC bundle as well as offer only 44 pin as well as larger TQFP chips, such as Xilinx’s CoolrunnerII.

Development environments

Most manufacturers offer a free advancement atmosphere that supports style entry utilizing simple schematics, in addition to Verilog or VHDL. many won’t support the latest FPGAs in the free version, however we only requirement the CPLD parts anyway. Altera has Quartus, Xilinx has ISE, as well as Lattice has ispLever. Atmel has ProChip designer for the ATF15xx series, however they only offer a 6month trial permit — which they wouldn’t really provide us.

Programmers

The advancement board we present doesn’t requirement a separate JTAG programmer since the pic microcontroller already programs the CPLD.  If you want an outside programmer, the cheapest are the parallel port programmers: Parallel cable III for Xilinx as well as BytleBlaster for Altera. affordable clones, as well as schematics, are offered at SparkFun.  The OpenOCD is a generic USB JTAG programmer that will work with many CPLDs, FPGAs, as well as ARMs.

Nossa escolha

We ultimately settled on the Xilinx XC9500XL series since it haD Um conjunto de avanço barato Podemos utilizar para testar nosso programador JTAG antes de implementar um desenho inteiro.

O DO-CPLD-DK de Digilent inclui um XC9572XL, um coolrunnerii, bem como programador de porta paralela. Nu Horizons tem alguns desenhos antigos não-rohs por US $ 40, no entanto, devido à manipulação de tipo de variável desleixada em seus scripts de processamento de cartões de crédito, não podemos totalizar um pedido on-line. Tentamos fazer isso por telefone, no entanto, eles se recusaram a tomar uma pequena ordem no telefone, mesmo durante um mau funcionamento do site. No final, era mais barato pagar o custo total em Digikey (# 122-1512-nd) depois de incluir as taxas de envio exorbitantes do Novo Horizonte. Nós normalmente não mencionaríamos isso, no entanto, com apenas dois locais para comprar o tabuleiro, provavelmente vale a pena notar nossa experiência.

Placa de avanço da CPLD.

Clique aqui para uma imagem esquemática de tamanho completo (PNG). O circuito, bem como o PCB, são projetados utilizando a versão freeware do CADSOFT Eagle. Todos os dados para este trabalho estão incluídos no arquivo de trabalho ligado no final do artigo.

O circuito

Um microcontrolador PIC 24FJ64GA002 (IC1) fornece o indivíduo, bem como a interface de programação para a CPLD. Utilizamos esta foto de US $ 4 em uma grande quantidade de empregos, já que o pino periférico escolhe a função torna o roteamento da placa verdadeiramente fácil. Inspecione nossa introdução ao PIC24F para mais detalhes. A foto precisa interagir com uma porta serial de PC, portanto, adicionamos um transceptor Max3232 RS232 acessível. A interface serial deve funcionar com um adaptador de serial USB->.

Nossa opção de CPLD (IC3), um xilinx xc9572xl (PDF), está ligado entre a foto, bem como vários outros componentes. Podemos produzir uma gama infinita de circuitos entre a foto, bem como outros chips utilizando a lógica reprogramável dentro da CPLD. O PIC programará a CPLD com código enviado a partir de uma porta serial do PC, no entanto, ainda trouxemos os pinos JTAG para um cabeçalho para uma depuração externa simples.

Um oscilador programável digital DS1085 (IC4) produz freqüências de relógio entre 8kHz, bem como 133MHz, em incrementos de 10kHz. Isso é extremamente semelhante ao DS1077 que cobrimos anteriormente, no entanto, tem até passos entre todas as freqüências. O DS1085 precisa de uma oferta de 5volt (VR2). A interface i2c também é executada a 5Volts, então vinculamos a 5Volt Tolerant Pic Pins. É possível utilizar o 3.3volt 66MHz 1085L em vez disso, além de eliminar a oferta de 5volt.

Utilizamos um regulador de tensão 3.3volt SOT223 barato (VR1) para alimentar a maior parte do circuito. O fornecimento de 5volt (VR2) pode ser excluído se você utilizar um oscilador mais lento 1085L 3.3volt.

As CPLDs são comumente utilizadas como controlador de memória, por isso incluímos 32k de SRAM (IC5) na placa de avanço. Uma trava de 3.3volt com entradas de 5Volt Tolerante interface as entradas de memória para uma ampla variedade de voltagens externas (IC6). As entradas de trava são mantidas baixas com uma rede de resistor de 1mohm (RN1). Vamos discutir esta seção extensivamente em um próximo artigo.

PCB.

O conselho é um design de quasi unilateral. Fizemos um número de compromissos para que possamos protótipo desse PCB extremamente experimental. Apresentamos o quadro “como é” para outros direitos que podem querer gravar esta placa em casa. Se você enviar o PCB para uma casa de tabuleiro, tente corrigir esses problemas antes de criar uma placa de dupla face ‘real’.

Um pino de energia da CPLD está faltando um capacitor de desacoplamento inteiramente; Não houve método para colocar um capacitor nessa área. Um capacitor de desacoplamento da CPLD, bem como o capacitor de desacoplamento de SRAM, são peças através do buraco. Utilizando essas partes através do buraco ficou livradas de alguns fios de jumper.

Os fios de jumper na parte de trás da placa são otimizados para a produção unilateral, em vez de grandes práticas de estilo. Falamos uma placa de dupla face soldando o barramento de potência nas costas. Um genuíno estilo de placa dupla face deve contar o barramento de energia para evitar que os caminhos de sinalização, bem como incluam os capacitores de desacoplamento ausentes.

Utilizamos uma tomada de microplaqueta de instalação do PLCC, no entanto, uma versão através do orifício é definitivamente uma ideia muito melhor. Nós, embora a versão SMD seria simples de soldar, no entanto [acabou por ser] um pesadelo. Nós realmente desejamos a CPLD para estar na frente do conselho para a melhor apresentação possível. Uma placa de dois lados apropriada com furos banhados pode ter uma tomada através do orifício na frente, no entanto, isso não foi possível com a nossa placa de protótipo de 1 lados.

Lista de peças

Clique aqui para um diagrama de colocação de tamanho completo (PNG).

Papel
Valor

Ic1.
PIC25FJ64GA002 (SOIC)

Ic2.
Max3232cse (SOIC-N)

Ic3.
Xc9572xl-10pcg44c (PLCC)

–
Soquete PLCC44, SMD

Ic4.
DS1085 ou DS1085L (SOIC)

Ic5.
32KX8, 3.3V, SRAM (SOJ)

Ic6.
74lvt573d (SOIC)

Vr1.
Regulador 3.3V, LD1117S33 (SOT223)

Vr2.
Regulador de 5V, LD1117S50 (SOT223)

C1-11,13-17.
0,1UF Decouspling Capacitores (0805)

C12.
Capacitor 0.01UF (0805)

C15,16.
0,1UF Decouspling Capacitores (através do buraco)

C18.
Capacitor de Tantalum 10UF (A)

R1,2.
Resistor 390OHM (0805)

R3-5.
Resistor 2000OHM (0805)

Rn1.
Rede de resistor de 1mohm (9 pinos)

LED1,2.
LED (08.05)

X1
db9 female serial port connector *untested

J1.
2.1mm power jack

ICSP, JTAG, SV1
0.1″ pin header, right angle

S1
Tactile switch (DTSM-6)

Firmware.

The firmware is written in C utilizing the free presentation version of the pic C30 compiler. discover all about working with this pic in our introduction to the pic 24F series. The firmware is included in the job archive at the end of the article.

We desired a super simple method to interact with the hardware on the board without endless compile-program-test cycles. We made a custom version of the Bus Pirate firmware that  provides a simple ASCII terminal interface to the DS1085 clock chip (I2C), the CPLD programing interface (JTAG), as well as a 3 cable (SPI) interface to the CPLD. inspect out the Bus Pirate tutorial for background on the simple syntax utilized with the firmware.

The original Bus Pirate firmware handles a number of protocols that share the exact same pins. For the CPLD version, we altered the pin assignments to in shape the connections on the advancement board. We likewise eliminated unused modules as well as options.

CPLD blinky LED examples

We prepared a number of styles in Xilinx’s ISE advancement environment. The schematics, pin placement files, as well as compiled styles (XSVF) are included in the job archive linked at the end of the article.  A full explanation of ISE is beyond the range of this article; we discovered the assist data sufficiently useful to make these examples.

The very first style just lights the LED linked to pin 8 of the CPLD.

Prepare the XSVF file

XSVF is a compressed JTAG programming format, as explained by Xilinx in this application note (PDF). XSVF isn’t restricted to programming Xilinx devices, as well as can be gotten ready for any type of chip that provides a typical BSDL JTAG meaning file.

Open the effect programming tool from the ISE style Suite job panel under Configure target device->iMPACT.

select the choice to produce a limit scan file,  as well as set the type to XSVF.

Give the XSVF output a data name as well as then add a compiled CPLD picture (ex1.jed) when prompted to add a device.

You should see a JTAG chain that contains a single device.

Click on the gadget as well as select program; effect will record the programming sequences to an XSVF file.

With XSVF data in hand, it’s time to open up a terminal as well as program the CPLD. We like Tera Term as well as Hercules on Windows. You must allow XON/XOFF flow manage in the client to utilize the JTAG interface. The default PC side setting for the advancement board terminal is 115200bps, 8N1.

HiZ>m <–select mode 1. Hiz. 2. I2C 3. JTAG 4. RAW3WIRE MODE>3 <–JTAG Conjunto de modo 900. 602 JTAG READY JTAG>(2) <–probe JTAG chain macro xxx JTAG INIT CHAIN xxx JTAGSM: RESET xxx JTAGSM: RESET->IDLE
xxx JTAGSM: IDLE->Instruction Register (DELAYED ONE bit FOR TMS)
xxx JTAGSM: IR->IDLE
xxx JTAGSM: IDLE->Data Register
xxx JTAGSM: DR->IDLE
xxx JTAGSM: RESET
xxx JTAGSM: RESET->IDLE
xxx JTAGSM: IDLE->Data Register
xxx JTAG CHAIN REPORT:
0x01 DEVICE(S)
#0x01 : 0xC9 0x02 0x06 0x9A <–XC9572XL responds xxx JTAGSM: DR->IDLE
JTAG>

In the terminal we go into the mode menu (m), as well as select JTAG (3). Macro 2 probes the JTAG chain, in our situation this is just the CPLD.  The chain report tells us that the chip is linked as well as responding. checked out more about the JTAG interface.

Now we can run the XSVF programmer, macro (3), as well as upload the XSVF data from the terminal in binary mode. The very first example just lights the LED on pin 8. If the LED lights, we can confirm that programming was successful. If your LED doesn’t light, don’t despair; sometimes the JTAG programmer sticks as well as a reset macro (1) will get the chip going.

LED at full brightness.

74LS32/4071 OR gate, blink at half rate (/2)

A major element of the CPLD advancement board is the 1085(L) frequency synthesizer linked to pin 7 of the CPLD. The next example utilizes a logic OR gate, like a 74LS32 or 4071 IC, to blink the LED whenever the clock signal is high. At even the slowest clock rate the blinking will be as well quick to see, however we should get a nice PWM dimming impact compared to the very first example.

JTAG>m <–select mode 1. Hiz. 2. I2C 3. JTAG 4. RAW3WIRE MODE>2 <–I2C interface to DS1085 Conjunto de modo 900. 202 I2C READY I2C>(1) <–address browse macro xxx browsing 7bit I2C address space. Encontrou gadgets em: 0xB0 0xB1 <–found the DS1085 address I2c>

Program the CPLD as before, as well as then switch to I2C mode to gain access to the DS1085 clock. We might look up the gadget address in th